S NAGA MALLESWARA REDDY

We have seen throughout this Electronics Tutorial section on Sequential Logic that a flip-flop will remain in one of its two stable states indefinitely until some form of triggering signal or pulse is applied to make it change to its other stable state. As flip-flops are bistable devices, these circuits are sometimes called latches because their outputs are locked or latched onto their input state until there is another input change.

We have also seen that the bistable flip-flop is the most basic storage element in a sequential logic circuit and can be configured to produce simple memory elements by interconnecting two inverting gates to generate feedback. Note that a combinational logic circuit does not require any form of memory and therefore does not use flip-flops. However, sequential logic circuits do have memory and therefore use various types of flip-flop designs to remember their present states.

The interconnection of digital logic gates to produce a memory device leads to applications such as switch debounce circuits, shift registers and counters, etc. Also, memory elements made from bistable latches form the basis of accumulators and registers on which a computer, or micro-controller, does its complex arithmetic.

The most basic way to create a single one-bit flip-flop is to use two NOR gates gates as shown. By using cross-coupled gates and feeding the output from one gate to the input of the other, (inputs-outputs interchanged) the circuit has a closed-loop (positive feedback) so its output depends on the state of the inputs, making the circuit sequential and having memory.

Flip-flops also belong to a category of digital switching circuits called Multivibrators. The basic bistable multivibrator is a type of regenerative circuit that has two active digital gates designed so that when one digital gate conducts, the other gate is cut-off and vice versa. These two digital gates produce two stable outputs both HIGH and LOW in which one is the complement of the other.

But we can make many different types of flip-flop circuits both asynchronous and synchronous (an asynchronous flip-flop does not require a clock signal input, but a synchronous one does) from either basic cross-coupled NAND Gates and NOR Gates with the conversion of flip-flops between the different types sometimes a bit confusion.

There are basically four different types of flip flops and these are:

• 1. Set-Reset (SR) flip-flop or Latch
• 2. JK flip-flop
• 3. D (Data or Delay) flip-flop
• 4. T (Toggle) flip-flop

So to help us understand better the different types of flip-flops available, the following sequential logic tutorial shows us how we can make the conversion of flip-flops from one type to another simply by modifying the inputs of a particular type of a flip-flop starting with the SR flip-flop.

The Set-Reset SR Flip-flop

The most basic of all the bistable latches and bistable multivibrators is the set-rest (SR) flip-flop. The basic SR flip-flop is an important bistable circuit because all the other types of flip-flop are built from it. The SR flip-flop is constructed using two cross-coupled digital NAND gates such as the TTL 74LS00, or two cross-coupled digital NOR gates such as the TTL 74LS02.

Generally SR bistables and flip-flops are said to be transparent because their outputs change or respond immediately to changes in their inputs. Also since they consist of digital logic gates along with feedback, SR flip-flops are regarded as asynchronous sequential logic circuits

The basic SR flip-flop has two inputs S (set) and R (reset) and two outputs Q and Q with one of these outputs being the complement of the other. Then the SR flip-flop is a two-input, two-output device. Consider the circuits below.

Basic NAND and NOR SR Flip-flops

Above are the two basic configurations for the asynchronous SR bistable flip-flop using either a negative input NAND gate, or a positive input NOR gate. For the SR bistable latch using two cross-coupled NAND gates operates with both inputs normally HIGH at logic level "1".

The application of a LOW at logic level "0" to the S input with R held HIGH causes output Q to go HIGH, setting the latch. Likewise, a logic level "0" on the R input with input S held HIGH causes the Qoutput to go LOW, resetting the latch. For the SR NAND gate latch, the condition of S = R = 0 is forbidden.

For the conversion of flip-flops using two cross-coupled NOR gates, when the output Q = 1 andQ = 0, the bistable latch is said to be in the Set state. When Q = 0 and Q = 1, the NOR gate latch is said to be in its Reset state. Then we can see that the operation of the NOR and NAND gate flip-flops are basically just the complements of each other.

The implementation of an SR flip-flop using two cross-coupled NAND gates requires LOW inputs. However, we can convert the operation of a NAND SR flip-flop to operate in the same manner as the NOR gate implementation with active HIGH (positive logic) inputs by using inverters, (NOT Gates) within the basic bistable design.

Then the conversion of flip-flops from active LOW to active HIGH inputs is given as:

Active HIGH Flip-flops

The basic SR flip flop above and its active HIGH equivalents, are all asynchronous type flip-flops, meaning that its inputs and present state alone determine the next state. But as one-bit memory storage device we may want it to hold its current output state regardless of what's happening to its two inputs and the operation of the basic SR flip-flop can be modified by including an additional input to control the behaviour of the bistable circuit.

The conversion of flip-flops basic circuit is achieved by using two additional AND gates which along with a control input, enable and disable the S and R inputs. This new circuit is called a Clocked or Gated SR Flip-flop.

The Gated Set-Reset (SR) Flip-flop

Gated SR flip-flops operate sequentially with its output state only changing in response to its inputs on the application of a clock or enable input. As the change to the output is controlled by this clock enable input, the gated SR flip-flop circuit is said to be a "synchronous" flip-flop. Then an asynchronous SR flip-flop requires no clock, but a synchronous one does.

The conversion of a standard NOR based SR flip-flop to a gated SR flip-flop is achieved using twoAND gates (TTL 74LS08) connected to the Set and Reset inputs. An additional control or "Enable" input, EN is connected to both AND gates, resulting in LOW outputs when the clock input is LOW as shown.

Gated SR Flip-flop Circuit

The clock or enable input, EN is connected to one of the inputs of both of the two AND gates, resulting in LOW outputs when the enable input is LOW (AND gate principals). Then any changes to inputs S or R has no affect on the state of the outputs, Q and Q of the flip-flop.

When the enable input is HIGH the two AND gates become transparent so any changes to the inputs S and R will change the state of the outputs as before. Then we can see that either a logic level "1" (HIGH) or a "0" (LOW) can be stored at the outputs of the gated flip-flop simply by applying a HIGH to the clock enable input, and that this output state can be retained for any desired period of time regardless of the condition of the inputs while the enable input remains LOW.

Gated Flip-flop Symbol

As the gated SR flip-flop is a three input device, the logic symbol shows three inputs: S, R and EN. The EN input is marked with a small triangle to denote the fact that the flip-flop responds to an edge or transition input.

The conversion of flip-flops to a clocked one is achieved by simply connecting this enable input to a timing signal. Any changes in the output state will occur in synchronisation with the clock CLK signal. Note that a clock signal is defined as a sequence of continuous pulses with each pulse having two separate states, the "ON" state and the "OFF" state, with its duty cycle representing its "ON" time divided by the total time period of pulse, ("ON" time + "OFF" time). Nearly all digital clock signals have a 50% duty cycle.

A clocked SR flip-flop can change state either on the rising positive-edge or on the falling negative-edge of the clock signal, or pulse. Therefore an edge-triggered flip-flop only responds or changes state when the clock pulse changes from one level to another. For example, HIGH to LOW or LOW to HIGH.

The output of a positive-edge triggered flip-flop only changes state on the rising edge (0-to-1) of the clock pulse and does not respond to the falling negative-edge. Likewise, a negative-edge triggered flip-flop changes state on the falling edge (1-to-0) of the clock pulse and does not respond to the rising positive-edge.

Gated SR Flip-flop with Preset and Clear

We can take this gated SR flip-flop circuit one step further to produce a bistable latch with additional inputs called Preset and Clear inputs which can be used to set a flip-flop to an initial state independent of the clock. Instead of the outputs Q and Q being loaded with an undefined value, we can over-ride all the inputs and preset the outputs to a defined state.

But why would we want to do that. Well when power is first applied to a flip-flop circuit, the initial logical state of the outputs can be completely random depending upon which logic gate latched first, then we would have no idea which switching state the flip-flop circuit is in. Therefore the initial state of the flip-flop would be uncertain as it may be in the SET state, (Q = 1) or it may be in the RESET state, (Q = 0).

Obviously this uncertainty in its switching is undesired as in the majority of applications we require the output to be set in a predefined state, either SET or RESET ready to accept data. But we can overcome this uncertainty with the conversion of flip-flops using two additional asynchronous inputs referred to as Preset, PR and Clear, CLR as shown.

Flip-flop with Preset and Clear Inputs

These additional inputs allow the flip-flop to be cleared, (Q = 0) whenever the CLEAR input is "0", and the PRESET input is "1". Likewise, the flip-flop can be preset to the logic "1" state whenever the PRESET input is "0" and the CLEAR input is "1". In this example, if the PRESET and CLEAR inputs are active HIGH (P = CLR = 1) then the circuit operates as a normal gated SR flip-flop circuit. Clearly both the PRESET and CLEAR inputs should not be made active LOW (P = C = 0) at the same time since this leads to an uncertain state.

This PRESET and CLEAR option is also handy to have if we want to put the flip-flop into a known set or reset state during a sequential operation ready for the next sequence.

The conversion of flip-flops from one type to another is easily implemented by either modifying the connections or using additional gates. As we have seen, the basic SR flip-flop has two inputs, S andR to store a single bit but to do this we must activate both of these inputs simultaneously. Moreover, the forbidden input combination of: S = R = 1 may occur accidentally, thus causing the SR flip-flop to switch into an undefined state.

To eliminate the need for two separate inputs and the possibility of the unintentional switching into an indeterminate state, by connecting an inverter (NOT gate) between the Set and Reset inputs, we can convert the basic RS flip-flop into a D-type flip-flop.

The (Data) D-type Flip-flop

The D-type flip-flop or Data Latch has only one input referred to as the "D", or data input, plus a clock input, CLK along with the usual two outputs, Q and Q. The D-type flip-flop transfers its digital data between the input and its outputs, after a delay of one clock pulse and so the "D" part is also referred to as a "delay" input.

D-type flip-flops are easily constructed from an SR flip-flop by simply connecting an inverter between the S and the R inputs so that the input to the inverter is connected to the S input and the output of the inverter is connected to the S input as shown.

The D-type Flip-flop

Two different circuits for the conversion of flip-flops to a D-type are given above. The top circuit is the traditional gated D-type configuration with the additional inverter. The bottom circuit functions in exactly the same manner but without the inverter, saving on one gate. As with all flip-flop configurations, D-type flip-flops can be implemented using NAND or NOR gates with or without the additional preset and clear.

The use of an inverter between the inputs ensures that the S and the R inputs are always a complement to each other eliminating the undefined condition of: S = R = 1. As a result, the D-type flip-flop is also known as a "transparent latch" as the output Q follows the D input when the clock input is HIGH, CLK = 1 transferring the binary information at the input directly to the output as if the flip-flop were not there, making it transparent.

The JK Flip-flop

The JK flip-flop is very similar in many ways to the previous SR flip-flop and is probably the most used of all the flip-flop designs. The terms "J" and "K" do not really mean or relate to any special description but where originally used at the time of the flip-flops initial development because these two letters are not used as part of any other digital device. For the JK flip-flop, the "J" is equivalent to Set and the "K" is equivalent to Reset.

We saw previously that the SR flip-flop has two or possibly three meaningful input combinations with the input sequence of S = R = 1 combination is not allowed but it can easily be modified to achieve different switching functions. Then the JK flip-flop is often considered to be a universal device.

The JK flip-flop has two inputs "J" and "K" so all four possible input configurations of: no change, set, reset and toggle are valid. With the "J" input acting like the "S" and the "K" input acting like the "R", it changes state when one of its inputs is HIGH. However, the beauty of the JK flip-flop is that when both "J" and "K" are HIGH at logic "1", the flip-flop toggles, that is changes from "0" to "1" or from "1" to "0" producing its own complement state.

JK Flip-flop Circuit

The conversion of flip-flops to a JK flip-flop is to cross connect the Q and Q outputs with the S and Rinputs through additional 3-input AND gates as shown.

If the J and K inputs are both HIGH, logic "1" then the Q output will change state (Toggle) for as long as the clock input, (CLK) is HIGH. Thus the output will be unstable creating a race-around problem with this basic JK circuit. This problem is avoided by ensuring that the clock input is at logic "1" only for a very short time, or to produce a more sophisticated JK flip-flop circuit called a Master–slave flip-flop.

The Master-Slave Flip-Flops

The conversion of flip-flops to a "Master-Slave" configuration involves the addition of a second bistable circuit. The master-slave configuration consists of two SR latches connected in cascade. One bistable flip-flop acts as the master receiving the external inputs while the other acts as its slave, taking its inputs directly from the master flip-flop as shown.

Basic Master-Slave Configuration

When the clock, CLK pulse goes HIGH, the data at the S and R inputs are transmitted through the master flip-flop, FFA as normal. The adjoining slave flip-flop, FFB however remains isolated since its clock input, CLK is LOW, logic "0" due to the inversion by the inverter.

Now when the initial clock pulse returns LOW to "0", the master becomes disabled and blocks the external data inputs from passing information to its outputs, whereas the slave flip-flop now becomes enabled and thus passes the latched information to its outputs at Q and Q. Then the clock input to the slave flip-flop is the complement of the clock input to the master flip-flop.

Master–slave flip-flops are referred to as level-triggered or pulse-triggered bistables because the input data is read during the entire time that the input clock pulse is at a HIGH level. Also, master-slave flip-flops are not restricted to SR master-slave only. There are JK master-slave and D-type master-slave flip-flops as well. In nearly all of them the slave flip-flop is a standard SR flip-flop, whereas the type of flip-flop takes its name from the master part which will be SR, JK or D-type configuration.

The (Toggle) T-type Flip-flop

The T-type (toggle) flip-flop is a single input bistable, with an operation similar to the D-type above. We saw above with the JK flip-flop configuration, that if J = K = 1 its output would toggle on the application of the next clock cycle. Then the conversion of flip-flops to a Toggle type is simply a matter of connecting the inputs HIGH.

The T-type flip-flop is not available commercially but can be constructed from a JK flip-flop (or D-type flip-flop) by connecting the J input with the K input and both to logic level "1". With J and KHIGH, the flip-flop changes state every time it is triggered at its clock input. This clock input is now called the "toggle input" as the output becomes "1" if it was "0", and a "0" if it was "1", that is it toggles.

Toggle T-type Flip-flop

The toggle flip-flop changes state when the clock input is applied, T = 1 and remains unchanged when T = 0. Then the transition from "0" to "1" will cause the output to toggle giving the flip-flop its name. The toggle T-type flip-flop is the basic building block of many digital circuits including frequency dividers and digital counters.

Toggle T-type flip-flops can be constructed from a JK flip-flop in two simple ways. In the first is that the J and K inputs can be tied together HIGH as shown with the clock input becoming the toggle as shown. The second way is with the J and K inputs tied together to provide the toggle input with the clock input remaining unchanged. The output toggles when T and CLK= or equal to "1". The output remains unchanged when T or CLK are LOW.

The Data D-type flip-flop can just like the JK flip-flop be converted to perform as a toggle flip-flop by connecting the Q output directly to the D-input with the toggling signal T being the clock input as shown above. Connecting the Q to the input creates negative feedback.

As the output from the toggle flip-flop changes state on every application of a clock signal, its output frequency is therefore one-half that of the input signal frequency thereby acting as a frequency divider. If more toggle flip-flops are cascaded together to form a chain, as the output of the first flip-flop acts as the clock for the second T flip-flop in the cascade arrangement, and the second flip-flop acts as the clock input for the third T flip-flop, etc, creating a frequency division along the chain.

Flip-flops and latches are by far the most fundamental building block of sequential logic circuits. Therefore, many IC manufacturers produce a wide variety of different flip-flop chips that use both the TTL and CMOS technologies as listed below.

Popular Types of Flip-flop IC's

Conversion of Flip-flops Summary

We have seen in this tutorial that a Bistable device is one in which two well defined states exist, and at any time the device could assume either of the stable states. The conversion of flip-flops from one type to another can be accomplished very easily as only slight modifications are required to convert one type to another. Flip-flops can be constructed using logic gate circuits with feedback.

We have also seen that flip-flops can have one, two or three inputs with one of those inputs connected to a clock signal. All flip-flops have two output states: Q = 1 and Q = 0 which changes in response to the application of the clock. For the SR latch, S = 1 sets Q to 1, and R = 1resets Q to 0.

The JK flip-flop is classed as a universal flip-flop and similar in design to the SR flip-flop in that when J = 1 it sets Q to 1, and when K = 1 it resetsQ to 0. The condition J = K = 1 causes Q to toggle.

All the flip-flops discussed above can have additional asynchronous CLEAR and PRESET inputs that cause Q to be cleared to a "0" or preset to a "1" independently of the clock signal.

D-type bistables can be construction from JK flip-flops by the addition of an inverter between the Jand K inputs. The D-type flip-flop is widely used in digital systems for transferring data and is said to be transparent, because any chance in input is immediately accepted and the output changes accordingly.

The T or toggle flip-flop changes state on the application of a clock pulse when T = 1, otherwise Qdoes not change. The toggle flip-flop is normally used for frequency division or for designing binary counters since binary counters require complementation. The toggle flip-flop is not commercially available but can be implemented by connecting the J and K inputs of a JK flip-flop together.

The conversion of flip-flops from one type to another is usually possible by reconfiguring the inputs, or by adding additional logic gates and we have seen that SR flip-flops can be converted to JK flip-flops which themselves can be converted to Data latches, and both the JK flip-flop and the D-type can be converted to a T-type toggle flip-flop.

The Sequential Ring Counter

In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a Serial-in to Serial-out Shift Register, the same sequence of data will exit from the last flip flip in the register chain after a preset number of clock cycles thereby acting as a sort of time delay circuit to the original input data signal.

But what if we were to connect the output of this Shift Register back to its input so that the output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then have a closed loop circuit that "recirculates" the same bit of DATA around a continuous loop for every state of its sequence, and this is the principal operation of a Ring Counter.

Then by looping the output back to the input, (feedback) we can convert a standard shift register circuit into a ring counter. Consider the circuit below.

4-bit Ring Counter

The synchronous Ring Counter example above, is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0". To achieve this, a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. This then places a single logic "1" value into the circuit of the ring counter.

So on each successive clock pulse, the counter circulates the same data bit between the four flip-flops over and over again around the "ring" every fourth clock cycle. But in order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0's" or all logic "1's" outputted at each clock cycle would make the ring counter invalid.

This type of data movement is called "rotation", and like the previous shift register, the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram:

Rotational Movement of a Ring Counter

Since the ring counter example shown above has four distinct states, it is also known as a "modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency.

The "MODULO" or "MODULUS" of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A "mod-n" ring counter will require "n" number of flip-flops connected together to circulate a single data bit providing "n" different output states.

For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require sixteen flip-flops. However, as in our example above, only four of the possible sixteen states are used, making ring counters very inefficient in terms of their output state usage.

Johnson Ring Counter

The Johnson Ring Counter or "Twisted Ring Counters", is another shift register with feedback exactly the same as the standard Ring Counter above, except that this time the inverted output Qof the last flip-flop is now connected back to the input D of the first flip-flop as shown below.

The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard ring counter then its modulo number is halved. So a "n-stage" Johnson counter will circulate a single data bit giving sequence of 2n different states and can therefore be considered as a "mod-2n counter".

4-bit Johnson Ring Counter

This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter, "0001"(1), "0010"(2), "0100"(4), "1000"(8) and repeat, the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0".

A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. For example, "1000", "1100", "1110", "1111", "0111", "0011", "0001", "0000" and this is demonstrated in the following table below.

Truth Table for a 4-bit Johnson Ring Counter

As well as counting or rotating data around a continuous loop, ring counters can also be used to detect or recognise various patterns or number values within a set of data. By connecting simple logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit can be made to detect a set number or value.

Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to divide the frequency of the clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs are also available.

For example, a 3-stage Johnson Ring Counter could be used as a 3-phase, 120 degree phase shift square wave generator by connecting to the data outputs at A, B and NOT-B.

The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used as a synchronous decade counter/divider circuit.

Other combinations such as the smaller 2-stage circuit which is also called a "Quadrature" (sine/cosine) Oscillator or Generator can be used to produce four individual outputs that are each 90 degrees "out-of-phase" with respect to each other to produce a 4-phase timing signal as shown below.

2-bit Quadrature Generator

As the four outputs, A to D are phase shifted by 90 degrees with regards to each other, they can be used with additional circuitry, to drive a 2-phase full-step stepper motor for position control or the ability to rotate a motor to a particular location as shown below.

Stepper Motor Control

2-phase (unipolar) Full-Step Stepper Motor Circuit

The speed of rotation of the Stepper Motor will depend mainly upon the clock frequency and additional circuitry would be require to drive the "power" requirements of the motor. As this section is only intended to give the reader a basic understanding of Johnson Ring Counters and its applications, other good websites explain in more detail the types and drive requirements of stepper motors.

Johnson Ring Counters are available in standard TTL or CMOS IC form, such as the CD4017 5-Stage, decade Johnson ring counter with 10 active HIGH decoded outputs or the CD4022 4-stage, divide-by-8 Johnson counter with 8 active HIGH decoded outputs.

The Shift Register is another type of sequential logic circuit that can be used for the storage or the transfer of data in the form of binary numbers. This sequential device loads the data present on its inputs and then moves or "shifts" it to its output once every clock cycle, hence the name "shift register".

A shift register basically consists of several single bit "D-Type Data Latches", one for each data bit, either a logic "0" or a "1", connected together in a serial type daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on.

Data bits may be fed in or out of a shift register serially, that is one after the other from either the left or the right direction, or all together at the same time in a parallel configuration.

The number of individual data latches required to make up a single Shift Register device is usually determined by the number of bits to be stored with the most common being 8-bits (one byte) wide constructed from eight individual data latches.

Shift Registers are used for data storage or for the movement of data and are therefore commonly used inside calculators or computers to store data such as two binary numbers before they are added together, or to convert the data from either a serial to parallel or parallel to serial format. The individual data latches that make up a single shift register are all driven by a common clock ( Clk ) signal making them synchronous devices.

Shift register IC's are generally provided with a clear or reset connection so that they can be "SET" or "RESET" as required. Generally, shift registers operate in one of four different modes with the basic movement of data through a shift register being:

• • Serial-in to Parallel-out (SIPO)  -  the register is loaded with serial data, one bit at a time, with the stored data being available at the output in parallel form.
• • Serial-in to Serial-out (SISO)  -  the data is shifted serially "IN" and "OUT" of the register, one bit at a time in either a left or right direction under clock control.
• • Parallel-in to Serial-out (PISO)  -  the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.
• • Parallel-in to Parallel-out (PIPO)  -  the parallel data is loaded simultaneously into the register, and transferred together to their respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can be presented graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same register thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right, (right shifting).

Serial-in to Parallel-out (SIPO) Shift Register

4-bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level "0" ie, no parallel data output.

If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0.

The second clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. The logic "1" has now moved or been "shifted" one place along the register to the right as it is now at QA.

When the third clock pulse arrives this logic "1" value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level "0" because the input to FFA has remained constant at logic level "0".

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of  0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of QA to QD.

Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows.

Basic Data Movement Through A Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will remain there provided clocking of the register has stopped. In practice the input data to the register may consist of various combinations of logic "1" and "0". Commonly availableSIPO IC's include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO) Shift Register

This shift register is very similar to the SIPO above, except were before the data was read directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow straight through the register and out of the other end. Since there is only one output, the DATA leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-Out Shift Registeror SISO.

The SISO shift register is one of the simplest of the four configurations as it has only three connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. Well this type of Shift Register also acts as a temporary storage device or it can act as a time delay device for the data, with the amount of time delay being controlled by the number of stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.

Parallel-in to Serial-out (PISO) Shift Register

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. The data is loaded into the register in a parallel format in which all the data bits enter their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then read out sequentially in the normal shift-right mode from the register at Q representing the data present atPA to PD.

This data is outputted one bit at a time on each clock cycle in a serial format. It is important to note that with this type of data register a clock pulse is not required to parallel load the register as it is already present, but four clock pulses are required to unload the data.

4-bit Parallel-in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format, it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO) Shift Register

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. The data is presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading and unloading is shown below.

4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections, the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary storage device or as a time delay device, with the amount of time delay being varied by the frequency of the clock pulses. Also, in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required.

Universal Shift Register

Today, there are many high speed bi-directional "universal" type Shift Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence the name "Universal".

These universal shift registers can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device. A commonly used universal shift register is the TTL 74LS194 as shown below.

4-bit Universal Shift Register 74LS194

Universal shift registers are very useful digital devices. They can be configured to respond to operations that require some form of temporary memory storage or for the delay of information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division.

Shift Register Tutorial Summary

Then to summarise a little about Shift Registers

• A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data bit.
• The output from each flip-Flop is connected to the D input of the flip-flop at its right.
• Shift registers hold the data in their memory which is moved or "shifted" to their required positions on each clock pulse.
• Each clock pulse shifts the contents of the register one bit position to either the left or the right.
• The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI).
• Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO).
• One application of shift registers is in the conversion of data between serial and parallel, or parallel to serial.
• Shift registers are identified individually as SIPO, SISO, PISO, PIPO, or as a Universal Shift Register with all the functions combined within a single device.

In the next tutorial about Sequential Logic Circuits, we will look at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop. This then produces another type of sequential logic circuit called a Ring Counter that are used as decade counters and dividers.